參數(shù)資料
型號(hào)： MPC106ARX66CG
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, CBGA304
封裝： 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁(yè)數(shù)： 31/32頁(yè)
文件大?。?/td> 451K
代理商： MPC106ARX66CG
8
Tsi106 PowerPC Host Bridge Hardware Specifications Manual
80C1000_MA002_02
Features
Secondary (L2) cache control
— Configurable for write-through or write-back operation
— Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte
— Up to 4 Gbytes of cacheable space
—Direct-mapped
— Supports byte parity
— Supports partial update with external byte decode for write enables
— Programmable interface timing
— Supports pipelined burst, synchronous burst, or asynchronous SRAMs
— Alternately supports an external L2 cache controller or integrated L2 cache module
Memory interface
— 1 Gbyte of RAM space, 16 Mbytes of ROM space
— Supports parity or error checking and correction (ECC)
— High-bandwidth, 64-bit data bus (72 bits including parity or ECC)
— Supports fast page mode DRAMs, extended data out (EDO) DRAMs, and synchronous
DRAMs (SDRAMs)
— Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 2 Mbyte to
128 Mbytes per bank
— ROM space may be split between the PCI bus and the 60x/memory bus (8 Mbytes each)
— Supports 8-bit asynchronous ROM or 64-bit burst-mode ROM
— Supports writing to Flash ROM
— Configurable external buffer control logic
— Programmable interface timing
PCI interface
— Compliant with PCI Local Bus Specification, Revision 2.1
— Supports PCI interlocked accesses to memory using LOCK signal and protocol
— Supports accesses to all PCI address spaces
— Selectable big- or little-endian operation
— Store gathering on PCI writes to memory
— Selectable memory prefetching of PCI read accesses
— Only one external load presented by the Tsi106 to the PCI bus
— Interface operates at 20–33 MHz
— Word parity supported
— 3.3 V/5.0 V-compatible
Support for concurrent transactions on 60x and PCI buses
Power management
— Fully-static 3.3-V CMOS design
— Supports 60x nap, doze, and sleep power management modes and suspend mode
IEEE 1149.1-compliant, JTAG boundary-scan interface
304-pin ceramic ball grid array (CBGA) package
相關(guān)PDF資料
PDF描述
MPC5200BV400 400 MHz, MICROPROCESSOR, PBGA272
MPC5200CBV266R2 266 MHz, MICROPROCESSOR, PBGA272
MPC5200CBV266BR2 266 MHz, MICROPROCESSOR, PBGA272
MPC5200BV400B 400 MHz, MICROPROCESSOR, PBGA272
MPC5200CBV400B 400 MHz, MICROPROCESSOR, PBGA272
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC106ARX66DE 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller
MPC106ARX66DG 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller
MPC106ARX66TE 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller
MPC106ARX66TG 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller
MPC106ARX83CE 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*