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參數(shù)資料
| 型號： | MPC106ARX66CG |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA304 |
| 封裝： | 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 451K |
| 代理商： | MPC106ARX66CG |
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32
Tsi106 PowerPC Host Bridge Hardware Specifications Manual
80C1000_MA002_02
Ordering Information
1.9.1.1.3 PLL Configuration
Table 18. Clock AC Timing Specifications
Num
Characteristic
SYSCLK/Core
33/66 MHz
SYSCLK/Core
33/83.3 MHz
Unit
Min
Max
Min
Max
—
60x processor bus (core) frequency
16.67
66
16.67
83.3
MHz
—
VCO frequency
150
400
150
400
MHz
—
SYSCLK frequency
16.67
33.33
16.67
33.33
MHz
1
SYSCLK cycle time
30.0
60.0
30.0
60.0
ns
2, 3
SYSCLK rise and fall time
—
2.0
—
2.0
ns
4
SYSCLK duty cycle measured at 1.4 V
40
60
40
60
%
—
SYSCLK jitter
—
±200
—
±200
ps
—
106 internal PLL relock time
—
100
—
100
μs
Table 19. PLL Configuration
PLL[0–3]1
Core/SYSCLK
Ratio
VCO
Multiplier
Core Frequency (VCO Frequency) in MHz
PCI Bus
16.6 MHz
PCI Bus
20 MHz
PCI Bus
25 MHz
PCI Bus
33.3 MHz
0010
1:1
x8
—
33.3 (266)
0101
2:1
x4
—
40 (160)
50 (200)
66.6 (266)
0110
5:2 2
x2
—
83.3 (166)
0111
5:2 2
x4
41.6 (166)
50 (200)
62.5 (250)
83.3 (333)
1000
3:1
x2
—
75 (150)
—
1001
3:1
x4
—
60 (240)
75 (300)
—
0011
PLL-bypass 3
PLL off
SYSCLK clocks core circuitry directly
1x core/SYSCLK ratio implied
1111
Clock off 4
PLL off
no core clocking occurs
Notes:
1
PLL[0–3] settings not listed are reserved. Some PLL configurations may select bus, CPU, or VCO frequencies which are
not useful, not supported, or not tested. See Section 1.4.2.1, “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
2
5:2 clock modes are only supported by Tsi106; earlier revisions do not support 5:2 clock modes. The 5:2 modes require
a 60x bus clock applied to the 60x clock phase (LBCLAIM) configuration input signal during power-on reset, hard reset,
and coming out of sleep and suspend power-saving modes.
3
In PLL-bypass mode, the SYSCLK input signal clocks the internal circuitry directly, the PLL is disabled, and the
core/SYSCLK ratio is set for 1:1 mode operation. This mode is intended for factory use and third-party tool vendors only.
Note also: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4
In clock-off mode, no clocking occurs inside the Tsi106 regardless of the SYSCLK input.
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