參數(shù)資料
型號(hào): MM908E621ACDWB
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror
中文描述: 綜合四半橋和三高的嵌入式微控制器和LIN高端側(cè)鏡
文件頁(yè)數(shù): 49/62頁(yè)
文件大?。?/td> 540K
代理商: MM908E621ACDWB
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
908E621
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E621, various
parameters (e.g. ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the “empty” ($FF) state:
$FD80:$FDDF Trim and Calibration Values
$FFFE:$FFFF Reset Vector
In the event the application uses these parameters, one
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
Trim Values
Below the usage of the trim values located in the flash
memory is explained
Internal Clock Generator (ICG) Trim Value
The internal clock generator (ICG) module is used to
create a stable clock source for the microcontroller without
using any external components. The untrimmed frequency of
the low frequency base clock (IBASE), will vary as much as
±25 percent due to process, temperature, and voltage
dependencies. To compensate this dependencies a ICG trim
values is located at address $FDC2. After trimming the ICG
is a range of typ. ±2% (±3% max.) at nominal conditions
(filtered (100nF) and stabilized (4,7uF) V
DD
= 5V,
T
Ambient
~25°C) and will vary over temperature and voltage
(V
DD
) as indicated in the 68HC908EY16 datasheet.
To trim the ICG this values has to be copied to the ICG
Trim Register ICGTR at address $38 of the MCU.
Important
The value has to copied after every reset.
Table 14. Window Clear Interval
Watchdog Period Range Value (AWD Trim)
The window watchdog supervises device recover from e.g.
code runaways.
The application software has to clear the watchdog within
the open window. Due to the high variation of the watchdog
period - and therefore the reduced width of the watchdog
window - a value is stored at address $FDCF. This value
classifies the watchdog period into 3 ranges (Range 0, 1, 2).
This allows the application software to select one out of three
time intervals to clear the watchdog based on the stored
value. The classification is done in a way that the application
software can have up to ±19% variation of the of optimal clear
interval, e.g. caused by ICG variation.
Effective Open Window
Having a variation in the watchdog period in conjunction
with a 50% open window results in effective open window,
which can be calculated by:
latest window open time: t_open = t_wd max / 2
earliest window closed time: t_closed = t_wd min
Optimal Clear Interval
The optimal clear interval - meaning the clear interval with
the biggest possible variation to latest window open time and
to the earliest window closed time can be calculated with the
following formula:
t_opt = t_open + (t_open+t_closed) / 2
See Table
14
to select the optimal clear interval for the
watchdog based on the Window No. and chosen period.
Window
Range
Period
Select bits
Watchdog Period
t_wd
Effective Open Window
Optimal Clear Interval
$FDCF
WDP1:0
min.
max.
Unit
t_open
t_closed
Unit
t_opt
Unit
max.
variation
0
00
68
92
ms
46
68
ms
57
ms
±19.3%
01
34
46
23
34
28.5
10
17
23
11.5
17
14.25
11
8.5
11.5
5.75
8.5
7.125
1
00
92
124
ms
62
92
ms
77
ms
±19.5%
01
46
62
31
46
38.5
10
23
31
15.5
23
19.25
11
11.5
15.5
7.75
11.5
9.625
2
00
52
68
ms
34
52
ms
43
ms
±20.9%
01
26
34
17
26
21.5
10
13
17
8.5
13
10.75
11
6.5
8.5
4.25
6.5
5.375
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MM908E621ACPEKR2 功能描述:8位微控制器 -MCU QUAD HB AND TRIPLE HS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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