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參數(shù)資料
| 型號： | MM24256-AWMN5T |
| 廠商： | 意法半導體 |
| 元件分類： | EEPROM |
| 英文描述： | 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| 中文描述： | 256千位串行總線EEPROM，帶有集成電路芯片使能兩線 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 124K |
| 代理商： | MM24256-AWMN5T |
M24256-A
8/20
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, themas-
ter sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
Minimizing System Delays by Polling On ACK
During theinternal writecycle, thememory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t
w
) is shown in Table 9, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Writeis in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle,no Ack willbe returned and the mas-
ter goes back to Step 1. If the memory has ter-
minated theinternal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byteof thisinstruction having been sent
during Step 1).
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE
Cycle
in Progress
AI01847
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random
Address
READ Operation
Send
Byte Address
First byte of
instruction
with RW = 0
already
decoded by M24xxx
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM24256-AWMN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| MM24256-AWMW5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| MM24256-AWMW6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| MM24256-BBN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| MM24256-BBN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
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