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參數(shù)資料
| 型號(hào)： | MM24256-AWMN5T |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 元件分類(lèi)： | EEPROM |
| 英文描述： | 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| 中文描述： | 256千位串行總線(xiàn)EEPROM，帶有集成電路芯片使能兩線(xiàn) |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大小： | 124K |
| 代理商： | MM24256-AWMN5T |
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M24256-A
6/20
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01120B
PAGE WRITE
(cont’d)
WC (cont’d)
S
DATA IN N
ACK
ACK
ACK
NO ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
NO ACK
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, theWC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256-A) are the same. If more
bytes are sentthan willfit up to the end of the row,
a condition known as ‘roll-over’ occurs.Data starts
to become overwritten (in a way not formally spec-
ified in this data sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
th
bit” time
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM24256-AWMN6T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| MM24256-AWMW5T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| MM24256-AWMW6T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines |
| MM24256-BBN5T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| MM24256-BBN6T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
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