參數(shù)資料
型號: MM24256-AWMN5T
廠商: 意法半導(dǎo)體
元件分類: EEPROM
英文描述: 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines
中文描述: 256千位串行總線EEPROM,帶有集成電路芯片使能兩線
文件頁數(shù): 1/20頁
文件大?。?/td> 124K
代理商: MM24256-AWMN5T
1/20
PRELIMINARY DATA
April 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24256-A
256 Kbit Serial
I
C Bus EEPROM
With Two Chip Enable Lines
I
Compatible with I
2
C Extended Addressing
I
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
I
Single Supply Voltage:
– 4.5V to 5.5V for M24256-A
– 2.5V to 5.5V for M24256-AW
– 1.8V to 3.6V for M24256-AR
I
2 Chip Enable Inputs: up to four memories can
be connected to the same I
2
C bus
I
Hardware Write Control
I
BYTE and PAGE WRITE (up to 64 Bytes)
I
RANDOM and SEQUENTIAL READ Modes
I
Self-Timed Programming Cycle
I
Automatic Address Incrementing
I
Enhanced ESD/Latch-Up Behavior
I
More than 100,000 Erase/Write Cycles
I
More than 40 Year Data Retention
DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits, and operate down to 2.5 V
(for the M24256-AW), and down to 1.8 V (for the
M24256-AR).
The M24256-A is available inPlastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages. The M24256-A is also available in
a chip-scale (SBGA) package.
Figure 1. Logic Diagram
AI02271C
SDA
VCC
M24256-A
WC
SCL
VSS
2
E0-E1
Table 1. Signal Names
E0, E1
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
PSDIP8 (BN)
0.25 mm frame
SO8 (MN)
150 mil width
TSSOP14 (DL)
169 mil width
8
1
8
1
14
1
SO8 (MW)
200 mil width
8
1
SBGA
SBGA7 (EA)
140 x 90 mil
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