參數(shù)資料
型號: MM24256-AWMN5T
廠商: 意法半導(dǎo)體
元件分類: EEPROM
英文描述: 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines
中文描述: 256千位串行總線EEPROM,帶有集成電路芯片使能兩線
文件頁數(shù): 3/20頁
文件大?。?/td> 124K
代理商: MM24256-AWMN5T
3/20
M24256-A
These memory devices are compatible with the
I
2
C extended memory standard. Thisis a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I
2
C bus definition.
The memory behaves as a slave device in the I
2
C
protocol, with all memory operations synchronized
by theserial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition isfollowed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: V
CC
Lock-Out Write Protect
In orderto prevent data corruptionand inadvertent
write operationsduring power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the V
CC
voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when V
CC
drops from the
operating voltage, belowthe POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slavesto synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to V
CC
. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though,this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
CC
. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Chip Enable (E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the two least significant
bits (b2, b1) of the 7-bit device select code.These
inputs must be tied to V
CC
or V
SS
to establish the
device select code. When unconnected, the E1
and E0 inputs areinternally read as V
IL
(see Table
7 and Table 8)
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. TheWrite Control signalis
used to enable (WC=V
IL
) or disable (WC=V
IH
)
write instructions to the entire memory area. When
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS(pF)
M
)
10
1000
fc = 400kHz
fc =100kHz
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