參數(shù)資料
型號(hào)： MM24128-BRBN6T
廠商： 意法半導(dǎo)體
元件分類： EEPROM
英文描述： 256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines
中文描述： 一百二十八分之二百五十六千位串行總線EEPROM，帶有集成電路芯片啟用三線
文件頁(yè)數(shù)： 8/19頁(yè)
文件大小： 117K
代理商： MM24128-BRBN6T
M24256-B, M24128-B
8/19
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to outputthe
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes fromconsecutive address-
es, with the internaladdress counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE
Cycle
in Progress
AI01847
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random
Address
READ Operation
Send
Byte Address
First byte of
instruction
with RW = 0
already
decoded by M24xxx
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