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參數(shù)資料
| 型號： | MM24128-BRBN6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| 中文描述： | 一百二十八分之二百五十六千位串行總線EEPROM，帶有集成電路芯片啟用三線 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大小： | 117K |
| 代理商： | MM24128-BRBN6T |
M24256-B, M24128-B
4/19
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP isidentified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between thememory deviceand the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls theSDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, theSDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change onlywhen the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition.Following this,themaster sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit DeviceSelect Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into:a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
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相關(guān)代理商/技術(shù)參數(shù) |
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| MM24128-BRDL5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| MM24128-BRDL6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| MM24128-BREA5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| MM24128-BREA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| MM24128-BRMN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
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