參數(shù)資料
型號(hào)： ML674000
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP128
封裝： 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-128
文件頁(yè)數(shù)： 5/39頁(yè)
文件大?。?/td> 247K
代理商： ML674000
PEDL674000-02
OKI Semiconductor
ML674000
13/39
Serial Interface
This LSI contains two channels of serial interface.
(1)
Start-stop synchronous serial interface without FIFO: 1 channel
This serial interface is incorporated in PLAT-7B.
(2)
Start-stop synchronous serial interface with 16-byte FIFO: 1 channel
This is ACE (Asynchronous Communication Element) equivalent in function to 16550A. It has 16-byte FIFO
in both sending and receiving.
PIO
This LSI contains two channels 16-bit parallel port.
(1)
Input or output can be selected for each bit.
(2)
Interrupt can be used for all 16 bits of each channel and interrupt is possible for each channel.
(3)
Interrupt mask and interrupt mode (level) can be set for all bits.
(4)
Input state immediately after reset.
AD Converter
Successive approximation type AD converter.
(1)
10 bits
× 8 channels
(2)
Sample hold function
(3)
Scan mode and select mode are supported
(4)
Interrupt is generated after completion of conversion.
(5)
Conversion time: shortest about 5 s.
DMAC
Two channels of direct memory access controller which transfers data between memory and memory, between I/O
and memory and between I/O and I/O.
(1)
Number of channels: 2 channels
(2)
Channel priority level: Fixed mode
Channel priority level is always fixed (channel 0 > 1).
Roundrobin
Priority level of the channel requested for transfer is kept lowest.
(3)
Maximum number of transfers: 65,536 times (64K times)
(4)
Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
(5)
Bus request system:
Cycle steal mode
Bus request signal is asserted for each DMA transfer cycle.
Burst mode:
Bus request signal is asserted until all transfers of transfer cycles are
complete.
(6)
DMA transfer request: Software request
By setting the software transfer request bit inside DMAC, the CPU starts DMA
transfer.
External request
DMA transfer is started by external request allocated to each channel.
(7)
Interrupt request:
Interrupt request is generated in CPU after the end of DMA transfers for the set number
of transfer cycles or after occurrence of error.
Interrupt request signal is output separately for each channel.
Interrupt request signal output can be masked for each channel.
相關(guān)PDF資料
PDF描述
ML674001TC 32-BIT, MROM, 33.333 MHz, RISC MICROCONTROLLER, PQFP144
ML67Q4002TC 32-BIT, FLASH, 33.333 MHz, RISC MICROCONTROLLER, PQFP144
ML67Q4002LA 32-BIT, FLASH, 33.333 MHz, RISC MICROCONTROLLER, PBGA144
ML674001LA 32-BIT, MROM, 33.333 MHz, RISC MICROCONTROLLER, PBGA144
ML67Q4051TC RISC MICROCONTROLLER, PQFP144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML674000-KIT 制造商:ROHM Semiconductor 功能描述:CMOS 32-Bit ARM-Based General-Purpose Single-Chip Microcontroller
ML674000LA 制造商:ROHM Semiconductor 功能描述:ML674000LAZ03A
ML674000LAZ03A-7 制造商:ROHM Semiconductor 功能描述:NEW PART NO ML674000LAZ0ARL 制造商:ROHM Semiconductor 功能描述:ML674000LAZ03A-7 - Bulk
ML674000LAZ0AL 制造商:ROHM Semiconductor 功能描述:ML674000LAZ0AL - Bulk
ML674000TBZ03A-7 制造商:ROHM Semiconductor 功能描述:Integrated Dual UART ARM7TDMI MCU 制造商:ROHM Semiconductor 功能描述:ARM7TDMI microprocessor integrated dual UART
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