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參數(shù)資料
| 型號： | ML674000 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 30/39頁 |
| 文件大?。?/td> | 247K |
| 代理商： | ML674000 |
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Rev.1.02
Jul 31, 2003
page 36 of 69
7560 Group (A version)
PULSE WIDTH MODULATION (PWM)
The 7560 group has a PWM function with an 8-bit resolution,
using f(XIN) or f(XIN)/2 as a count source.
Data Setting
The PWM output pins are shared with ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255 (n+1)/f(XIN)
= 31.875 (n+1) s (when f(XIN) = 8 MHz)
Output pulse “H” period = PWM period m/255
= 0.125 (n+1) m s
(when f(XIN) = 8 MHz)
PWM Operation
When either bit 1 (PWM0 function enable bit) or bit 2 (PWM1 func-
tion enable bit) of the PWM control register or both bits are
enabled, operation starts from initializing status, and pulses are
output starting at “H”. When one PWM output is enabled and that
the other PWM output is enabled, PWM output which is enabled to
output later starts pulse output from halfway of PWM period (see
Figure 37).
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Fig. 34 Timing of PWM cycle
Fig. 35 Block diagram of PWM function
31.875 m (n+1)
255
s
T = [31.875 (n+1)] s
PWM output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(XIN) = 8 MHz)
Data bus
Count source
selection bit
“0”
“1”
PWM
prescaler pre-latch
PWM
register pre-latch
PWM
prescaler latch
PWM
register latch
Transfer control circuit
PWM circuit
1/2
XIN
PWM0 function
enable bit
P51 /PWM1
PWM prescaler
PWM1 function
enable bit
Port P51
lacth
Port P50
lacth
P50 /PWM0
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