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PEDL674000-02
OKI Semiconductor
ML674000
6/39
Primary Function
Secondary Function
Pin
Symbol
Type
Description
Symbol
Type
Description
80
XA[11]
O
External memory access address output port
—
81
XA[12]
O
External memory access address output port
—
82 GND_CORE GND GND for CORE
—
83 VDD_CORE VDD Power supply for CORE
—
84
XA[13]
O
External memory access address output port
—
85
XA[14]
O
External memory access address output port
—
86
XA[15]
O
External memory access address output port
—
87
XA[16]
O
External memory access address output port
—
88
XA[17]
O
External memory access address output port
—
89
GND_IO
O
GND for I/O
—
90
XA[18]
O
External memory access address output port
—
91
PIOA[10]
I/O
General port (with interrupt function)
XA[19]
O
External memory access address output port
92
PIOA[11]
I/O
General port (with interrupt function)
XA[20]
O
External memory access address output port
93
PIOA[12]
I/O
General port (with interrupt function)
XA[21]
O
External memory access address output port
94
VDD_IO
VDD Power supply for I/O
95
PIOA[13]
I/O
General port (with interrupt function)
XA[22]
O
External memory access address output port
96
PIOA[14]
I/O
General port (with interrupt function)
XA[23]
O
External memory access address output port
97
PIOA[15]
I/O
General port (with interrupt function)
XWR
O
Transfer direction of external bus
98
XOE_N
O
Output enable (excluding SDRAM)
—
99
XWE_N
O
Write enable
—
100 GND_IO
GND GND for I/O
101 XBWE_N[0]
O
Byte write enable (LSB)
—
102 XBWE_N[1]
O
Byte write enable (MSB)
—
103 XROMCS_N
O
External ROM chip select
—
104 XRAMCS_N
O
External RAM chip select
—
105 XIOCS_N[0]
O
IO bank 0 chip select
—
106 XIOCS_N[1]
O
IO bank 1 chip select
—
107 GND_CORE GND GND for CORE
—
108 VDD_CORE VDD Power supply for CORE
—
109
PIOB[0]
I/O
General port (with interrupt function)
DREQ0
I
DMA request signal (CH0)
110
PIOB[1]
I/O
General port (with interrupt function)
DREQCLR0
O
DREQ clear signal (CH0)
111
VDD_IO
VDD Power supply for I/O
—
112
PIOB[2]
I/O
General port (with interrupt function)
DREQ1
I
DMA request signal (CH1)
113
PIOB[3]
I/O
General port (with interrupt function)
DREQCLR1
O
DREQ clear signal (CH1)
114
PIOB[4]
I/O
General port (with interrupt function)
TCOUT0
O
DMAC Terminal Count (CH0)
115
PIOB[5]
I/O
General port (with interrupt function)
TCOUT1
O
DMAC Terminal Count (CH1)
116 GND_IO
GND GND for I/O
—
117
PIOB[6]
I/O
General port (with interrupt function)
PWMOUT[0]
O
PWM output (CH0)
118
PIOB[7]
I/O
General port (with interrupt function)
PWMOUT[1]
O
PWM output (CH1)
119 XBS_N[0]
O
External bus byte select (LSB)
—
120 XBS_N[1]
O
External bus byte select (MSB)
—