參數(shù)資料
型號： ML674000
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP128
封裝： 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-128
文件頁數(shù)： 16/39頁
文件大?。?/td> 247K
代理商： ML674000
Rev.1.02
Jul 31, 2003
page 23 of 69
7560 Group (A version)
Fig. 18 Interrupt control
Fig. 19 Structure of interrupt-related registers
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection bit of A-D control reg-
ister (bit 6 of address 3416)
When not requiring for the interrupt occurrence synchronous with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (polarity switch bit) or the inter-
rupt source selection bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request acceptance
b7
b0
Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
Not used (“0” at reading)
(INTEDGE : address 003A16)
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer 1 interrupt request bit
INT2 interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (“0” at reading)
(IREQ2 : address 003D16)
Interrupt control register 2
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer 1 interrupt enable bit
INT2 interrupt enable bit
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (“0” at reading)
(Write “0” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
b7
b0
b7
b0
0
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