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參數(shù)資料
| 型號： | ML674000 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 39/39頁 |
| 文件大?。?/td> | 247K |
| 代理商： | ML674000 |
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PEDL674000-02
OKI Semiconductor
ML674000
9/39
Pin
Number
Pin Name
I/O
Description
Primary/
Secondary
Logic
External bus control signals
103
XROMCS_N
O
ROM bank chip select
—
Negative
104
XRAMCS_N
O
SRAM bank chip select
—
Negative
105
XIOCS_N[0]
O
I/O bank 0 chip select
—
Negative
106
XIOCS_N[1]
O
I/O bank 1 chip select
—
Negative
98
XOE_N
O
Output enable/read enable
—
Negative
99
XWE_N
O
Write enable
—
Negative
119-120
XBS_N[1:0]
O
Byte select: XBS_N[1] for MSB; XBS_N[0] for LSB
—
Negative
101
XBWE_N[0]
O
LSB write enable
—
Negative
102
XBWE_N[1]
O
MSB write enable
—
Negative
97
XWR
O
Data transfer direction for external bus, used when
connecting to Motorola I/O devices. This represents the
secondary function of pin PIOA[15], produced by setting bit 7
in the port control (GPCTL) register to "1."
Secondary
—
121
XWAIT
I
External I/O bank 0 WAIT signal.
This input permits access to devices slower than register
settings.
Secondary
Positive
External bus control signals (DRAM)
123
XRAS_N
O
Row address strobe. Used for both EDO DRAM and SDRAM.
Secondary
Negative
122
XCAS_N
O
Column address strobe signal (SDRAM)
Secondary
Negative
124
XSDCLK
O
SDRAM clock (same frequency as internal system clock)
Secondary
—
126
XSDCKE
O
Clock enable (SDRAM)
Secondary
—
125
XSDCS_N
O
Chip select (SDRAM)
Secondary
Negative
1
XDQM[1]/XCAS_N[1]
O
Connected to SDRAM: DQM (MSB)
Connected to EDO DRAM: column address strobe signal
(MSB)
Secondary
Positive
2
XDQM[0]/XCAS_N[0]
O
Connected to SDRAM: DQM (LSB)
Connected to EDO DRAM: column address strobe signal
(LSB)
Secondary
Positive
DMA control signals
109
DREQ0
I
Ch 0 DMA request signal, used when DMA controller
configured for DREQ type
Secondary
Positive
110
DREQCLR0
O
Ch 1 DREQ signal clear request. The DMA device responds
to this output by negating DREQ.
Secondary
Positive
114
TCOUT0
O
Indicates to Ch 0 DMA device that last transfer has started
Secondary
Positive
112
DREQ1
I
Ch 1 DMA request signal, used when DMA controller
configured for DREQ type
Secondary
Positive
113
DREQCLR1
O
Ch 1 DREQ signal clear request. The DMA device responds
to this output by negating DREQ.
Secondary
Positive
115
TCOUT1
O
Indicates to Ch 1 DMA device that last transfer has started
Secondary
Positive
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PDF描述 |
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