參數(shù)資料
型號(hào): ML60851EGA
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù): 24/88頁
文件大?。?/td> 1137K
代理商: ML60851EGA
Oki Semiconductor
ML60851E
28/84
Interrupt Status Register (INTSTAT)
Read address
DCh
Write address
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
After a bus reset
See
below
0
See
below
See
below
0
Definition
Setup Ready Interrupt Status:
When bit D0 of the interrupt enable register (INTENBL) is “1”, the content
of bit D0 of the EP0 status register (EP0STAT) is copied here.
This bit is “0” when D0 of INTENBL is “0”. In other words, when the eight
bytes of setup data are received in the setup stage of control transfer and are
correctly stored in the setup registers, this bit is set to “1” and the
INTR pin is
asserted.
EP1 Packet Ready Interrupt Status: When bit D1 of the interrupt enable register (INTENBL) is “0” (ednpoint 1
interrupt is masked), the content of this bit is “0” and hence no interrupt is
generated.
When endpoint 1 is configured as a receive endpoint (EP1CON D7=0), if bit
D1 of the interrupt enable register (INTENBL) is “1” (EP1 interrupt enabled),
the content of bit D1 of the endpoint packet ready register (PKTRDY) is
copied here.
When endpoint 1 is configured as a transmit endpoint (EP1CON D7=1), if
bit D1 of the interrupt enable register (INTENBL) is “1” (EP1 interrupt
enabled), the inverted (NOT) content of bit D5 of the endpoint pakcet ready
register (PKTRDY) is copied here.
In other words, when endpoint 1 packet ready interrupt (D1 of INTENBL)
has been enabled the following statements become true:
Setup Ready Interrupt Status
EP1 Packet Ready Interrupt
Status
EP2 Packet Ready Interrupt
Status
EP0 Receive Packet Ready
Interrupt Status
EP0 Transmit Packet Ready
Interrupt Status
USB Bus Reset Interrupt Status
Suspend State Interrupt Status
EP3 Packet Ready Interrupt Status
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