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參數資料
| 型號： | ML60851EGA |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數： | 11/88頁 |
| 文件大?。?/td> | 1137K |
| 代理商： | ML60851EGA |
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Oki Semiconductor
ML60851E
17/84
EP1 Receive Packet Ready Bit (D1)
This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D1 bit.
The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and the packet
ready bits are present independently for layer A and layer B. The switching between these two layers is done
automatically by the ML60851E. For detailed description of double layered FIFO operation, please refer to page
77 of this manual.
Bit name
Asserting condition
Action when asserted
EP1 Receive packet ready (D1)
When an error-free packet is
received in either layer A or layer B.
The local MCU can read the
EP1RXFIFO. EP1 is locked when
both layer A and layer B have
received a packet data.
Bit name
Deasserting condition
Action when deasserted
EP1 Receive packet ready (D1)
When the local MCU resets (writes a
“1”) in the bits of both layer A and
layer B.
Reception is possible in EP1 when at
least one of the bits of layer A and
layer B has been reset.
See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.
EP2 Receive Packet Ready Bit (D2)
This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D2 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
Asserting condition
Action when asserted
EP2 Receive packet ready (D2)
When an error-free packet is
received.
EP2 is locked. In other words, an
NAK is returned automatically when
a data packet is received from the
host computer.
Bit name
Deasserting condition
Action when deasserted
EP2 Receive packet ready (D2)
When the local MCU resets (writes a
“1” in) this bit.
Data reception is possible in EP2.
EP0 Transmit Packet Ready Bit (D4)
This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D4 bit.
The conditions of asserting and deasserting this bit are the following.
Bit name
Asserting condition
Action when asserted
EP0 Transmit packet ready (D4)
When the local MCU sets this bit.
Data transmission is possible from
EP0.
Bit name
Deasserting condition
Action when deasserted
EP0 Transmit packet ready (D4)
1. When an ACK is received from the
host computer in response to the
data transmission from EP0.
2. When a setup packet is received.
EP0 is locked. In other words, an
NAK is returned automatically when
an IN token is received from the host
computer.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ML60851ETB | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
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