參數(shù)資料
型號(hào): MK30X256VMD100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 54/72頁
文件大?。?/td> 1847K
代理商: MK30X256VMD100R
Table 40. I2S master mode timing (continued)
Num
Description
Min.
Max.
Unit
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
5 x tSYS
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-2.5
ns
S7
I2S_BCLK to I2S_TXD valid
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
ns
S1
S2
S3
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 27. I2S timing — master mode
Table 41. I2S slave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
8 x tSYS
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
ns
S14
I2S_FS input hold after I2S_BCLK
3
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
ns
S17
I2S_RXD setup before I2S_BCLK
10
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
58
Preliminary
Freescale Semiconductor, Inc.
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