6.3.1 MCG specifications
Table 13. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25°C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
TBD
—
A
tirefsts
Internal reference (slow clock) startup time
—
TBD
4
s
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
—
± 0.1
± 0.3
%fdco
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
± 0.2
± 0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+ 0.5
- 1.0
± 3.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.5
± TBD
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
—
4
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
3
—
5
MHz
Iintf
Internal reference (fast clock) current
—
TBD
—
A
tirefstf
Internal reference startup time (fast clock)
—
TBD
s
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
kHz
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
Mid range (DRS=01)
1280 × ffll_ref
40
41.94
50
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60
62.91
75
MHz
High range (DRS=11)
2560 × ffll_ref
80
83.89
100
MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
25