參數(shù)資料
型號: MK30X256VMD100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 51/72頁
文件大小: 1847K
代理商: MK30X256VMD100R
Table 37. Master mode DSPI timing (high-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DS1
DSPI_SCK output cycle time
2 x tBCLK
ns
DS2
DSPI_SCK output high/low time
(tSCK/2) 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) 2
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) 2
ns
DS5
DSPI_SCK to DSPI_SOUT valid
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
2
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
ns
DS3
DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data
Data
Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 24. DSPI classic SPI timing — master mode
Table 38. Slave mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
12.5
MHz
DS9
DSPI_SCK input cycle time
4 x tBCLK
ns
DS10
DSPI_SCK input high/low time
(tSCK/2) 2
(tSCK/2 + 2
ns
DS11
DSPI_SCK to DSPI_SOUT valid
TBD
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
ns
DS15
DSPI_SS active to DSPI_SOUT driven
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
14
ns
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
55
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