MDS213
Data Sheet
97
Zarlink Semiconductor Inc.
CPU Reads FCB
CPU write the read command into CPUIRCMD with FCB Handle, W/R=0. And set C_RDY. Also, set the
table type = FCB, (CPUIRCMD[14]=1)
Frame Engine puts the specified FCB content into CPUIRDATL and CPUIRDATM
Frame Engine Clear C_RDY
Frame Engine set CPUIRRDY[0] to notify CPU that the FCB data is ready to be read.
CPU writes FCB
CPU writes the content of FCB into CPUIRDATL and CPUIRDATM
CPU writes the handle of FCB into CPUIRCMD [9:0], set CPUIRCMD [10] = 1,(write CMD), set
CPUIRCMD[31]=1, CMD_RDY and set the Table Index to FCB, (CPUIRCMD[14]=1).
Frame Engine clears CPUIRCMD [31], C_RDY, when Frame Engine reads FCB done
Apply the similar method to access the other four tables.
18.2.11.8 CPUIRCMD - CPU Internal RAM Command Register
Access:
Non-Zero-Wait-State,
Direct Access,
Write/Read
Address:
h584
Command for CPU accesses five internal Tables
Bit [9:0]
Entry Index
The index of specified entry
Type = MCID(16)
Entry index[3:0]
Type = VMAP(256)
Entry index[7:0]
Type = BMCT(1K)
Entry index[9:0]
Type = FCB(1K)
Entry index[9:0]
Type = QCNT (64)
Entry index[5:0]
Bit [10]
W/R
Write or Read the table entry
0=Read
1=Write
Bit[15:11]
Table bit map
Bit maps of five tables.
Bit[11]
MCID
MCID=1 Use MC ID l Table
Bit[12]
VMAP
VMAP=1 Use VLAN port mapping Table (VMAP)
Bit[13]
BMCT
BMCT=1 Use Buffer Manager Control Table (BM control)
Bit[14]
FCB
FCB=1 Use FCB Table
Bit[15]
QCNT
QCNT=1 Use Transmission Queue control Table (QM control)
Bit [30:16] Reserve
Bit [31]
C_RDY
Command Ready
0=Not Ready
1=Ready
0
30
16 15 14 13 12 11 10 9
QC FC
B
NT
CT
Entry Index [9:0]
BM
C_R
DY
VM
AP
MC
ID
W/
R
31