參數(shù)資料
型號: MDS213
廠商: Zarlink Semiconductor Inc.
英文描述: 12-Port 10/100Mbps + 1Gbps Ethernet Switch
中文描述: 12口10/100Mbps千兆以太網(wǎng)交換機
文件頁數(shù): 18/120頁
文件大?。?/td> 1678K
代理商: MDS213
MDS213
Data Sheet
18
Zarlink Semiconductor Inc.
# = Active low signal
Input = Input signal
In-ST = Input signal with Schmitt-Trigger
Output = Output signal (Tri-State driver)
Out-OD = Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD = Input & Output signal with Open-Drain driver
U = Internal weak pull-up
TS = Tri-state
ST = Schmitt Trigger
Frame Buffer Interface
Ball No(s)
Symbol
I/O
Description
AB2, AB1, Y4,
AA3, AA2, AA1,
W5, W4, Y3, Y2,
Y1, W3, V4, W2,
W1, V3, U5, U4,
V2, V1, U3, U2, T4,
U1, T3, T2, T1, R4,
R3, R2, R1, R5,
L2, L3, K1, L4, K2,
K3, M5, J1, J2, K4,
J3, H1, K5, H2, J4,
H3, G1, G2, G3,
H4, F1, F2, H5, F3,
G4, E1, E2, D1,
F4, E3, D2, E4
L_D[63:0]
I/O-TS, U
Frame Buffer - Data Bit [63:0]
A2, A3, B3, C4,
D5, E6, B4, C5,
D6, A4, B5, E8, A5,
D7, C6, B6, A6, D8
L_A[20:3]
Output
Frame Buffer - Address Bit [20:3]
D3
L_CLK
Output
Frame Buffer Clock
N2
L_ADS#
Output
Frame Buffer Address Status Control
P3, P4, P1, P2, N1,
N3, N4, M1
L_BW[7:0]#
Output
Frame Buffer Individual Byte Write Enable
[7:0]
M3, L1
L_WE[1:0]#
Output
Frame Buffer Write Chip Select [1:0]
M4, M2
L_OE[1:0]#
Output
Frame Buffer Read Chip Select [1:0]
Ball No(s)
RMII ETHERNET ACCESS PORTS [11:0]
AB23
M_MDC
Output
MII Management Data Clock - (Common for
all RMII Ports [11:0])
AB24
M_MDIO
I/O-TS
MII Management Data I/O - (Common for all
RMII Ports [11:0])
AA4
M_CLKI
Input
Reference Input Clock
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