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參數(shù)資料
| 型號(hào)： | MDS213 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 12-Port 10/100Mbps + 1Gbps Ethernet Switch |
| 中文描述： | 12口10/100Mbps千兆以太網(wǎng)交換機(jī) |
| 文件頁數(shù)： | 38/120頁 |
| 文件大小： | 1678K |
| 代理商： | MDS213 |
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MDS213
Data Sheet
38
Zarlink Semiconductor Inc.
7.4.1 CPU-HISC Communication Using Queues
The first communication mechanism is a pair of Input and Output Queues between HISC and management CPU.
The management CPU input/output queue is a very efficient mechanism for a single 32-bit data exchange between
the HISC and management CPU. In general, a management frame, i.e., Bridged Data Protocol Units (BDPU), is
forwarded directly from the HISC to the management CPU via the CPU Output Queue. Small management
requests, less than 24 bits, are delivered to the HISC via the CPU Input Queue.
7.4.2 Mailbox
The second communication mechanism is a hardware mailbox that can support variable size messages,
exchanged between the management CPU and the HISC. A major use of the mailbox is to exchange information
required for updating the switching database.
7.4.3 CPU-HISC MAIL
When the management CPU sends a mail message to the HISC, the CPU acquires an address of a free mail from
the free mail list (via register AFML). It then writes the mail content to the given memory address. Afterward, it
sends the mail to the HISC via the Mailbox Access (AMBX) Register. Whenever a management mail message is
received, an event is generated to inform the HISC to process the mail message.
7.4.4 HISC-CPU Mail
When a mail message arrives from the HISC, the mailbox hardware sends an interrupt, namely "Mail Arrive"
(MAIL_ARR) to the CPU. The CPU can then access the mail via the Mailbox Access Register (AMBX). At this point,
the CPU reads the mail handle and retrieves the contents of the mail from the AMBX Register.
8.0 The XPipe
The XPipe provides a high-speed link between systems utilizing two MDS213 devices. The XPipe incorporates a
32-bit-wide data pipe, with a high-speed point-to-point connections, and a full-duplex interface between devices.
While operating at a 100MHz, this interface can provide 3.2G bits per second (Gbps) of bandwidth per pipe in both
directions.
8.1 XPipe Connection
Figure 8 - XPipe System Block Diagram for the MDS213
Transmit FIFO
Receive FIFO
X_DO[31:0]
X_DCLKO
X_DENO
X_DI[31:0]
X_DCLKI
X_DENI
Xmit
Ctrl
Rcvd
Ctrl
Source
Receive FIFO
Transmit FIFO
X_DI[31:0]
X_DCLKI
X_DENI
X_DO[31:0]
X_DCLKO
X_DENO
X_FCI
X_FCO
Recd
Ctrl
Xmit
Ctrl
X_FCO
X_FCI
Target
Target
Source
MDS213
MDS213
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