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參數(shù)資料
| 型號(hào)： | MCM16Y1BGCFT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 93/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | MCM16Y1BGCFT16 |
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MOTOROLA
MC68HC16Y1
58
MC68HC16Y1TS/D
BERR and DATA8 control the state of this register following reset. If BERR and/or DATA8 are low during
reset, this register is set to $00, defining all port E pins to be I/O pins. If BERR and DATA8 are both high
during reset, the register is set to $FF, which defines all port E pins to be bus control signals.
3.8.3 Port F
Port F pins can be configured as interrupt request inputs, edge-detect input/outputs, or discrete input/
outputs. When port F pins are configured for edge detection, and a priority level is specified by writing
a value to the Port F edge-detect interrupt level register (PFLVR), port F control logic generates an in-
terrupt request when the specified edge is detected. Interrupt vector assignment is made by writing a
value to the Port F edge-detect interrupt vector register (PFIVR). The edge-detect interrupt has the low-
est arbitration priority in the SCIM.
A write to the port F data register is stored in the internal data latch, and if any port F pin is configured
as an output, the value stored for that bit is driven on the pin. A read of PORTF returns the value on a
pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the
data register.
Port F is a single register that can be accessed in two locations. It can be read or written at any time,
including when the MCU is in emulator mode.
The bits in this register control the direction of Port F pin drivers when the pins are congured for I/O.
Setting any bit in this register congures the corresponding pin as an output. Clearing any bit in this reg-
ister congures the corresponding pin as an input.
The elds in this register determine the functions of pairs of port F pins as shown in the following tables.
BERR and DATA9 determine the reset state of this register. If BERR and/or DATA9 are low during reset,
this register is set to $00, dening all port F pins to be I/O pins. If BERR and DATA9 are both high during
reset, the register is set to $FF, which denes all port F pins except PF0 to be interrupt signals.
PORTF — Port F Data Register
$YFFA19, $YFFA1B
76543210
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
UUUUUUUU
DDRF — Port F Data Direction Register
$YFFA1D
76543210
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
RESET:
00000000
PFPAR — Port F Pin Assignment Register
$YFFA1F
76543210
PFPA3
PFPA2
PFPA1
PFPA0
RESET (Expanded, Single-chip):
DATA9
00000000
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