參數(shù)資料
型號(hào): MCM16Y1BGCFT16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封裝: QFP-160
文件頁(yè)數(shù): 117/138頁(yè)
文件大?。?/td> 784K
代理商: MCM16Y1BGCFT16
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MOTOROLA
MC68HC16Y1
8
MC68HC16Y1TS/D
1.3 Address Map
The internal address map of the MC68HC16Y1 is shown below. Although there are 24 intermodule bus
(IMB) address lines, the CPU16 uses only ADDR[19:0]. ADDR[23:20] follow the logic state of ADDR19
— addresses $080000 to $F7FFFF are not accessible. The RAM array is positioned by the base ad-
dress register in the RAM CTRL block. Reset disables the RAM array. Unimplemented blocks are
mapped externally.
Figure 3 MC68HC16Y1 Address Map
In the address map, Y = M111, where M is the modmap signal state on the IMB. M reflects the state of
the modmap bit in the module configuration register of the single-chip integration module. In the
MC68HC16Y1, Y must equal $F — if M is cleared, IMB modules will be inaccessible until a reset occurs.
M can be written only once after reset.
1.4 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate design of modular microcon-
trollers. It contains circuitry to support exception processing, address space partitioning, multiple inter-
rupt levels, and vectored interrupts. The standardized modules in the MC68HC16Y1 communicate with
one another and with external components via the IMB. Although the full IMB supports 24 address and
16 data lines, the MC68HC16Y1 uses only 16 data lines and 20 address lines. Because the CPU16
uses only 20 address lines, ADDR[23:20] are tied to ADDR19 when processor driven. ADDR[23:20] are
brought out to pins for test purposes.
"Y1 MEMORY MAP"
ADC
64 BYTES
ROM CTRL
32 BYTES
GPT
64 BYTES
SCIM
128 BYTES
SRAM CTRL
64 BYTES
MCCI
64 BYTES
TPU
512 BYTES
$YFFFFF
$YFFE00
$YFFC3F
$YFFC00
$YFFB3F
$YFFB00
$YFFA7F
$YFFA00
$YFF93F
$YFF900
$YFF83F
$YFF820
$YFF73F
$YFF700
48K ROM ARRAY
(MAPPED TO ANY 64K BOUNDARY)
2K SRAM ARRAY
(MAPPED TO 2K BOUNDARY)
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