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參數(shù)資料
| 型號(hào)： | MCM16Y1BGCFT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 18/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | MCM16Y1BGCFT16 |
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MOTOROLA
MC68HC16Y1
114
MC68HC16Y1TS/D
PDS — Standby Power Status Bit
0 = Loss of standby power.
1 = No loss of standby power
The RAM array can be powered by a standby power source (VSTBY) while VDD to the microcontroller is
turned off. PDS indicates when VSTBY has fallen below a reference level for a specified period of time.
To detect power loss, software must first set PDS, then monitor its state during normal operation and
following reset.
RASP[1:0] — RAM Array Space Field
o = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space.
This bit limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 in the MC68HC16Y1 operates in supervisor mode only, RASP
has no effect.
TRAMTST — RAM Test Register
$YFFB02
TRAMTST is used for factory test of the TPURAM module.
TRAMBAR is used to specify an array base address in the system memory map. This prevents acci-
dental remapping of the array. TRAMBAR can be written only once after reset.
TRAMBAR[15:3] — RAM Array Base Address Field
This field specifies bits [23:11] of the array base address. The array must be enabled in order to be ac-
cessed. Since the states of ADDR[23:20] follow the state of ADDR19 in the MC68HC16Y1, addresses
in the range $080000 to $F7FFFF cannot be accessed.
RAMDS — RAM Array Disable Status Bit
0 = RAM array is enabled
1 = RAM array is disabled
RAMDS indicates whether the array is active or disabled. The array is disabled after reset. Writing a
valid base address into RAMBAR automatically clears RAMDS and enables the array.
8.3 TPURAM Operation
There are six TPURAM operating modes, as follows.
The RAM module is in normal mode when powered by VDD. The array can be accessed by byte, word,
or long word. A byte or aligned word (high-order byte is at an even address) access only takes one bus
cycle or two system clocks. A long word or misaligned word access requires two bus cycles.
Standby mode is intended to preserve RAM contents when VDD is removed. SRAM contents are main-
tained by VSTBY. Circuitry within the SRAM module switches to the higher of VDD or VSTBY with no loss
of data. When SRAM is powered by VSTBY, access to the array is not guaranteed.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous
reset occurs while a byte or word SRAM access is in progress, the access will be completed. If reset
occurs during the first word access of a long-word operation, only the first word access will be complet-
ed. If reset occurs during the second word access of a long word operation, the entire access will be
completed. Data being read from or written to the RAM may be corrupted by asynchronous reset.
TRAMBAR — RAM Base Address and Status Register
$YFFB04
16
3
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
NOT
USED
RAMDS
RESET:
0
1
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