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參數(shù)資料
| 型號(hào)： | MCM16Y1BGCFT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 76/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | MCM16Y1BGCFT16 |
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MOTOROLA
MC68HC16Y1
42
MC68HC16Y1TS/D
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the table below.
3.3.2 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DSACKx) and during IACK cycles (AVEC). The monitor asserts BERR if response time is excessive.
DSACKx and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACKx response on the external bus unless it initiates the bus cycle. The
BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a system
contains external bus masters, an external bus monitor must be implemented, and the internal to exter-
nal bus monitor option must be disabled.
3.3.3 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus, caused by a double bus fault.
This signal is asserted by the CPU after a double bus fault occurs. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the DBE bit in the SYPCR.
3.3.4 Spurious Interrupt Monitor
The spurious interrupt monitor causes a bus error exception if no interrupt arbitration occurs during in-
terrupt acknowledge cycle.
3.3.5 Software Watchdog
Register shown with read value.
The software watchdog is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a
service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog
times out and issues a reset. This register can be written at any time, but returns zeros when read.
Perform a software watchdog service sequence as follows:
Write $55 to SWSR.
Write $AA to SWSR.
BMT
Bus Monitor Time-out Period
00
64 System Clocks
01
32 System Clocks
10
16 System Clocks
11
8 System Clocks
SWSR — Software Service Register
$YFFA27
76543210
SWSR
RESET:
00000000
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