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參數(shù)資料
| 型號(hào)： | MCM16Y1BACFT16 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 89/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | MCM16Y1BACFT16 |
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MOTOROLA
MC68HC16Y1
54
MC68HC16Y1TS/D
External interrupt requests are routed to the CPU16 through the external bus interface and SCIM inter-
rupt control logic. The CPU treats external interrupt requests as though they had come from the SCIM.
External IRQ[6:1] are active-low level-sensitive inputs. External IRQ7 is an active-low transition-sensi-
tive input. It requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive to prevent redun-
dant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted,
and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending re-
quests are processed at instruction boundaries or when exception processing of higher-priority excep-
tions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the
CPU does not recognize the occurrence of the request in any way.
3.7.1 Interrupt Acknowledge and Arbitration
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 de-
tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs
a CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the inter-
rupt source. The mask value also serves two purposes: it is latched into the CCR IP field to mask lower-
priority interrupts during exception processing, and it is decoded by modules that have requested inter-
rupt service to determine whether the current interrupt acknowledge cycle pertains to them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle. If their requests are at the specified IP level, they respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by serial con-
tention between module interrupt arbitration (IARB) field bit values.
Each module that can make an interrupt service request, including the SCIM, has an IARB field in its
configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111
(highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt
exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SCIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SCIM is %1111. The re-
set IARB value for all other modules is %0000. Initialization software must assign different IARB values
to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same nonzero
value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle to is not driven on the external bus unless the
SCIM wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be termi-
nated by a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM16Y1BGCFT16 | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| M68HC16Y1CFC | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| MCV14AI/SL | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| MCV14ATI/SL | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| MCV14AI/P | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM16Z2BCFC16 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC16B1 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC20 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC20B1 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
| MCM16Z2BCFC25 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
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