參數(shù)資料
型號: MCM16Y1BACFT16
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封裝: QFP-160
文件頁數(shù): 97/138頁
文件大?。?/td> 784K
代理商: MCM16Y1BACFT16
MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
61
Chip select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits — multiple chip selects assigned to the same address and
control must have the same number of wait states. Chip selects can also be synchronized with the
ECLK signal available on ADDR23.
When a memory access occurs, chip select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip select registers. If all parameters match, the appropriate chip select signal is asserted. Select sig-
nals are active low. A block diagram of a chip select circuit is shown below.
Figure 7 Chip Select Circuit Block Diagram
If a chip select function is given the same address as a microcontroller module or memory array, an
access to that address will go to the module or array, and the chip select signal will not be asserted.
Each chip select pin can have two or more functions. Chip select configuration out of reset is determined
by operating mode. In all modes, the boot ROM select signal is automatically asserted out of reset. In
single-chip mode, all chip select pins except CS10 and CS0 are configured for alternate functions or
discrete output. In expanded modes, appropriate pins are configured for chip select operation, but chip
select signals cannot be asserted until a transfer size is chosen. In fully expanded mode, data bus pins
can be held low to enable alternate functions for chip select pins.
The following table shows allocation of chip selects and discrete outputs to MCU pins.
CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
1 OF 12
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