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| 型號(hào)： | MCM16Y1BACFT16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 68/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | MCM16Y1BACFT16 |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
35
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog continues to run.
1 = When FREEZE is asserted, the software watchdog is disabled.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the periodic interrupt timer counters continue to run.
1 = When FREEZE is asserted, the periodic interrupt timer counters are disabled, preventing inter-
rupts during software debug.
CPUD — CPU Development Support Disable
0 = Instruction pipeline signals available on pins IPIPE0 and IPIPE1
1 = Pins IPIPE0 and IPIPE1 placed in high-impedance state unless a breakpoint occurs
CPUD iscleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode.
SLVE — Slave Mode Enable
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
This bit is a read-only status bit that reflects the state of DATA11 during reset. Slave mode is used for
factory testing. Reset state is the complement of DATA11 during reset in fully expanded mode.
SHEN[1:0] — Show Cycle Enable
This field determines what the external bus interface does with the external bus during internal transfer
operations. A show cycle allows internal transfers to be externally monitored. The table below shows
whether show cycle data is driven externally, and whether external bus arbitration can occur. To prevent
bus conflict, external peripherals must not be enabled during show cycles.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places SCIM global registers in either supervisor data space or user data space. Since
the CPU16 in the MC68HC16Y1 operates only in supervisory mode, SUPV has no effect.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
The logic state of M determines the value of ADDR23 in the IMB module address. Because AD-
DR[23:20] follow the state of ADDR19 in the MC68HC16Y1, M must be set to one — if M is cleared,
IMB modules will be inaccessible. This bit can be written only once after reset.
ABD — Address Bus Disable
0 = Pins ADDR[2:0] operate normally.
1 = Pins ADDR[2:0] are disabled.
ABD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode. ABD
can be written only once after reset.
SHEN
Action
00
Show cycles disabled, external arbitration enabled
01
Show cycles enabled, external arbitration disabled
10
Show cycles enabled, external arbitration enabled
11
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
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| MCM16Y1BGCFT16 | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| M68HC16Y1CFC | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| MCV14AI/SL | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| MCV14ATI/SL | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| MCM16Z2BCFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC16B1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC20 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC20B1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
| MCM16Z2BCFC25 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
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