參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 97/170頁
文件大?。?/td> 1562K
代理商: MCIMX31
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
97
Preliminary
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
Figure 38. SDRAM Refresh Timing Diagram
SD13
Data setup time
tDS
2.0
ns
SD14
Data hold time
tDH
1.3
ns
1
SD11 and SD12 are determined by SDRAM controller register settings.
Table 36. SDRAM Refresh Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD1
SDRAM clock high-level width
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level width
tCL
3.4
4.1
ns
Table 35. SDR SDRAM Write Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS
CAS
WE
RAS
ADDR
DQ
DQM
BA
ROW/BA
SD6
SD7
SD11
SD10
SD10
SDCLK
SD1
SD2
SDCLK
SD3
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