參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 110/170頁
文件大?。?/td> 1562K
代理商: MCIMX31
i.MX31/i.MX31L Advance Information, Rev. 1.4
110
Freescale Semiconductor
Preliminary
Electrical Characteristics
The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and
V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,
SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA
channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters
are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC
Registers.
Figure 51
depicts the synchronous display interface timing for access level, and
Table 49
lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Figure 51. Synchronous Display Interface Timing Diagram—Access Level
Table 49. Synchronous Display Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min
Typ
1
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
2
Display interface clock down time
Max
Units
IP16
Display interface clock
low time
Tckl
Tdicd-Tdicu-1.5
Tdicd
2
-Tdicu
3
3
Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Tdicd-Tdicu+1.5
ns
IP17
Display interface clock
high time
Tckh
Tdicp-Tdicd+Tdicu-1.5
Tdicp-Tdicd+Tdicu
Tdicp-Tdicd+Tdicu+1.5
ns
IP18
Data setup time
Tdsu
Tdicd-3.5
Tdicu
ns
IP19
Data holdup time
Tdhd
Tdicp-Tdicd-3.5
Tdicp-Tdicu
ns
IP20
Control signals setup
time to display interface
clock
Tcsu
Tdicd-3.5
Tdicu
ns
IP19
DISPB_D3_CLK
DISPB_DATA
IP18
IP20
DISPB_D3_VSYNC
DISPB_D3_HSYNC
IP17
IP16
DISPB_D3_DRDY
other controls
Tdicd
1
2
--
THSP_CLKceil2 DIHSP_CLK_PERIOD
=
Tdicu
1
2
--
THSP_CLKceil2 HSP_CLK_PERIOD
=
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