參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 85/170頁
文件大小: 1562K
代理商: MCIMX31
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
85
Preliminary
Figure 24. Read Data Latch Cycle Timing DIagram
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Table 31. NFC Target Timing Parameters
ID
Parameter
Symbol
Relationship to NFC clock
Period (T)
Unit
Min
Max
Min
Max
NF1
NFCLE Setup Time
tCLS
T
45
ns
NF2
NFCLE Hold Time
tCLH
T
45
ns
NF3
NFCE Setup Time
tCS
T
90
ns
NF4
NFCE Hold Time
tCH
T
45
ns
NF5
NF_WP Pulse Width
tWP
T
45
ns
NF6
NFALE Setup Time
tALS
T
45
ns
NF7
NFALE Hold Time
tALH
T
45
ns
NF8
Data Setup Time
tDS
T
90
ns
NF9
Data Hold Time
tDH
T
45
ns
NF10 Write Cycle Time
tWC
2T
90
ns
NF11 NFWE Hold Time
tWH
T
45
ns
NF12 Ready to NFRE Low
tRR
6T
270
ns
NF13 NFRE Pulse Width
tRP
1.5T
67.5
ns
NF14 READ Cycle Time
tRC
2T
90
ns
NF15 NFRE High Hold Time
tREH
0.5T
22.5
ns
NF16 Data Setup on READ
tDSR
15
ns
NF17 Data Hold on READ
tDHR
5
ns
NFCLE
NFCE
NFRE
NFRB
NFIO[15:0]
Data from NF
NF13
NF15
NF14
NF17
NF12
NF16
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