參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 139/170頁
文件大?。?/td> 1562K
代理商: MCIMX31
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
139
Preliminary
4.3.20.2
Reset Sequence
4.3.20.2.1
Cards with Internal Reset
The sequence of reset for this kind of SIM Cards is as follows (see
Figure 76
):
After powerup, the clock signal is enabled on SGCLK (time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles
after T0.
Figure 76. Internal-Reset Card Reset Sequence
4.3.20.2.2
Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see
Figure 77
):
1. After powerup, the clock signal is enabled on CLK (time T0)
2. After 200 clock cycles, RX must be high.
3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on
RX during those 40000 clock cycles)
4. RST is set High (time T1)
Table 58. SIM Timing Specification—High Drive Strength
Num
Description
Symbol
Min
Max
Unit
1
SIM Clock Frequency (CLK)
1
1
50% duty cycle clock
2
With C = 50pF
3
With C = 50pF
S
freq
0.01
5 (Some new cards
may reach 10)
MHz
2
SIM CLK Rise Time
2
S
rise
20
ns
3
SIM CLK Fall Time
3
S
fall
20
ns
4
SIM Input Transition Time (RX, SIMPD)
S
trans
25
ns
SVEN
CLK
RX
2
T0
1
response
2
1
< 200 clock cycles
< 40000 clock cycles
400 clock cycles <
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