參數(shù)資料
型號(hào): MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁(yè)數(shù): 91/108頁(yè)
文件大小: 1235K
代理商: MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
91
Table 56. SSI Transmitter with Internal Clock Timing Parameters
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
ns
SS2
(Tx/Rx) CK clock high period
36.0
ns
SS3
(Tx/Rx) CK clock rise time
6
ns
SS4
(Tx/Rx) CK clock low period
36.0
ns
SS5
(Tx/Rx) CK clock fall time
6
ns
SS6
(Tx) CK high to FS (bl) high
15.0
ns
SS8
(Tx) CK high to FS (bl) low
15.0
ns
SS10
(Tx) CK high to FS (wl) high
15.0
ns
SS12
(Tx) CK high to FS (wl) low
15.0
ns
SS14
(Tx/Rx) Internal FS rise time
6
ns
SS15
(Tx/Rx) Internal FS fall time
6
ns
SS16
(Tx) CK high to STXD valid from high impedance
15.0
ns
SS17
(Tx) CK high to STXD high/low
15.0
ns
SS18
(Tx) CK high to STXD high impedance
15.0
ns
SS19
STXD rise/fall time
6
ns
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
10.0
ns
SS43
SRXD hold after (Tx) CK falling
0
ns
SS52
Loading
25
pF
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