參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 15/108頁
文件大?。?/td> 1235K
代理商: MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
15
4.2.1
Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up
logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of
POR.
Figure 2
shows the power-up sequence.
NOTE
Stages need to be performed in the order shown; however,
within
each stage,
supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1,
and NVCC3 through NVCC10 do not need to be powered up in the order shown.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Figure 2. Power-Up Sequence
4.2.2
Powering Down
The power-down sequence should be completed as follows:
1. Lower the FUSE_VDD supply.
2. Lower the remaining supplies.
Release
POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
FVCC, MVCC,
SVCC, UVCC
NVCC2, NVCC21, NVCC22
FUSE_VDD
Hold POR Asserted
1
1
1, 2
1
1
1, 3
Notes:
1
The board design must guarantee that supplies reach 90% level before transition
to the next state, using Power Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD
has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions.
3
It is allowable for FVCC, MVCC, SVCC, and UVCC to be up after FUSE_VDD.
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