參數(shù)資料
型號(hào)： MCIMX31_07
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Multimedia Applications Processors
中文描述： 多媒體應(yīng)用處理器
文件頁(yè)數(shù)： 47/108頁(yè)
文件大?。?/td> 1235K
代理商： MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
47
Figure 37. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
NOTE
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
Table 35
indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
4.3.10
ETM Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that
supports TRACECLK frequencies up to 133 MHz.
Figure 38
depicts the TRACECLK timings of ETM, and
Table 36
lists the timing parameters.
Figure 38. ETM TRACECLK Timing Diagram
Table 35. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD21 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS).
tDQSQ
–
0.85
ns
SD22 DQS DQ HOLD time from DQS
tQH
2.3
–
ns
SD23 DQS output access time from SDCLK posedge
tDQSCK
–
6.7
ns
SDCLK
SDCLK
DQS (input)
DQ (input)
Data
Data
Data
Data
Data
Data
Data
Data
SD23
SD21
SD22
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