參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應用處理器
文件頁數(shù): 89/108頁
文件大?。?/td> 1235K
代理商: MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
89
4.3.22
SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing
information:
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX signals when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
4.3.22.1
SSI Transmitter Timing with Internal Clock
Figure 79
depicts the SSI transmitter timing with internal clock, and
Table 56
lists the timing parameters.
SJ11
TCK low to TDO high impedance
44
ns
SJ12
TRST assert time
100
ns
SJ13
TRST set-up time to TCK low
40
ns
1
On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2
V
M -
mid point voltage
Table 55. SJC Timing Parameters (continued)
ID
Parameter
All Frequencies
Unit
Min
Max
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