參數(shù)資料
型號： MCIMX31_07
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Multimedia Applications Processors
中文描述： 多媒體應(yīng)用處理器
文件頁數(shù)： 49/108頁
文件大小： 1235K
代理商： MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
49
4.3.13
This section describes the electrical information of the I
2
C Module.
I
2
C Electrical Specifications
4.3.13.1
Figure 40
depicts the timing of I
2
C module.
Table 39
lists the I
2
C module timing parameters where the I/O
supply is 2.7 V. 1
I
2
C Module Timing
Figure 40. I
2
C Bus Timing Diagram
Table 39. I
2
C Module Timing Parameters—I
2
C Pin I/O Supply=2.7 V
ID
Parameter
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
IC1
I2CLK cycle time
10
–
2.5
–
μ
s
IC2
Hold time (repeated) START condition
4.0
–
0.6
–
μ
s
IC3
Set-up time for STOP condition
4.0
0
1
–
0.6
0
1
–
μ
s
IC4
Data hold time
1
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
2
The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
3
A Fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time
(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I
2
C-bus specification)
before the I2CLK line is released.
4
C
b
= total capacitance of one bus line in pF.
3.45
2
0.9
2
μ
s
IC5
HIGH Period of I2CLK Clock
4.0
–
0.6
–
μ
s
IC6
LOW Period of the I2CLK Clock
4.7
–
1.3
–
μ
s
IC7
Set-up time for a repeated START condition
4.7
–
0.6
100
3
–
μ
s
IC8
Data set-up time
250
–
–
ns
IC9
Bus free time between a STOP and START condition
4.7
–
1.3
–
μ
s
IC10
Rise time of both I2DAT and I2CLK signals
–
1000
20+0.1C
b4
20+0.1C
b4
–
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
–
300
300
ns
IC12
Capacitive load for each bus line (C
b
)
–
400
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
START
I2DAT
I2CLK
IC1
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