參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 22/108頁
文件大?。?/td> 1235K
代理商: MCIMX31_07
i.MX31/i.MX31L Advance Information, Rev. 2.3
22
Freescale Semiconductor
Electrical Characteristics
4.3.5.2
PIO Mode Timing
Figure 9
shows timing for PIO read, and
Table 21
lists the timing parameters for PIO read.
Figure 9. PIO Read Timing Diagram
tco
propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
12.0 ns
tsu
set-up time
ata_data
to bus clock L-to-H
8.5 ns
tsui
set-up time
ata_iordy
to bus clock H-to-L
8.5 ns
thi
hold time
ata_iordy
to bus clock H to L
2.5 ns
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
7 ns
tskew2
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
transceiver
tskew3
Max difference in buffer propagation delay for any of following signals
ata_iordy, ata_data
(read)
transceiver
tbuf
Max buffer propagation delay
transceiver
tcable1
cable propagation delay for
ata_data
cable
tcable2
cable propagation delay for control signals
ata_dior, ata_diow, ata_iordy, ata_dmack
cable
tskew4
Max difference in cable propagation delay between
ata_iordy
and
ata_data (read)
cable
tskew5
Max difference in cable propagation delay between (
ata_dior, ata_diow, ata_dmack)
and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
cable
tskew6
Max difference in cable propagation delay without accounting for ground bounce
cable
1
Values provided where applicable.
Table 20. ATA Timing Parameters (continued)
Name
Description
Value/
Contributing Factor
1
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