參數(shù)資料
型號: MCHC705P6ACSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù): 97/130頁
文件大?。?/td> 1541K
代理商: MCHC705P6ACSDR2
Capture/Compare Timer
Timer I/O Registers
MC68HC705P6A — Rev. 2.0
Advance Information
MOTOROLA
Capture/Compare Timer
69
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Resets clear the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Resets clear the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic 1 or logic 0
appears on the TCMP pin when a successful output compare occurs.
Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
相關PDF資料
PDF描述
MC68HC705P6AMP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6P 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6DW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6S 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
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