參數(shù)資料
型號: MCHC705P6ACSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù): 123/130頁
文件大?。?/td> 1541K
代理商: MCHC705P6ACSDR2
Mask Option Register (MOR)
Advance Information
MC68HC705P6A — Rev. 2.0
92
Mask Option Register (MOR)
MOTOROLA
COP — COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will
reset the MCU if the timeout period is reached before the COP
watchdog timer is cleared by the application software and the voltage
applied to the IRQ/VPP pin is between VSS and VDD. Clearing the
COP bit will disable the COP watchdog timer regardless of the voltage
applied to the IRQ/VPP pin.
LEVEL — IRQ Edge Sensitivity
If the LEVEL bit is clear, the IRQ/VPP pin will only be sensitive to the
falling edge of the signal applied to the IRQ/VPP pin. If the LEVEL bit
is set, the IRQ/VPP pin will be sensitive to both the falling edge of the
input signal and the logic low level of the input signal on the IRQ/VPP
pin.
LSBF — SIOP Least Significant Bit First
If the LSBF bit is set, the serial data to and from the SIOP will be
transferred least significant bit first. If the LSBF bit is clear, the serial
data to and from the SIOP will be transferred most significant bit first.
Address: $1EFF
Bit 7
6
54321
Bit 0
Read:
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Write:
Erased State:
00
000000
Address: $1F00
Bit 7
6
54321
Bit 0
Read:
SECURE
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
Write:
Erased State:
00
000000
= Unimplemented
Figure 11-1. Mask Option Register (MOR)
相關(guān)PDF資料
PDF描述
MC68HC705P6AMP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6P 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6DW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6S 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
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