參數(shù)資料
型號(hào)： MCHC705P6ACSDR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù)： 91/130頁
文件大小： 1541K
代理商： MCHC705P6ACSDR2
Serial Input/Output Port (SIOP)
SIOP Registers
MC68HC705P6A — Rev. 2.0
Advance Information
MOTOROLA
Serial Input/Output Port (SIOP)
63
will 1) abort the transmission, 2) reset the serial bit counter, and 3)
convert the port B/SIOP port to a general-purpose I/O port. Reset
clears the SPE bit.
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.
The MSTR bit is readable and writeable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit as well as the
SPE bit, disabling the SIOP subsystem.
7.4.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits. Figure
7-4 shows the position of each bit in the register and indicates the value
of each bit after reset.
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is
Address:
$000B
Bit 7
6
54321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00
000000
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
相關(guān)PDF資料
PDF描述
MC68HC705P6AMP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6P 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6DW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6S 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
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