參數(shù)資料
型號: MCHC705P6ACSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù): 111/130頁
文件大?。?/td> 1541K
代理商: MCHC705P6ACSDR2
Analog Subsystem
A/D Status and Control Register (ADSC)
MC68HC705P6A — Rev. 2.0
Advance Information
MOTOROLA
Analog Subsystem
81
obtained. See 9.3.2 Reference Voltage (VREFH) for more
information.
ADON — A/D Subsystem On
When the A/D subsystem is turned on (ADON = 1), it requires a time,
tADON, to stabilize before accurate conversion results can be attained.
CH2–CH0 — Channel Select Bits
CH2, CH1, and CH0 form a 3-bit field which is used to select an input
to the A/D converter. Channels 0–3 correspond to port C input pins
PC6–PC3. Channels 4–6 are used for reference measurements.
Channel 7 is reserved. If a conversion is attempted with channel 7
selected, the result will be $00. Table 9-1 lists the inputs selected by
bits CH0-CH3.
If the ADON bit is set and an input from channels 0–4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port
C pin an input). If the port C data register is read while the A/D is on
and one of the shared input channels is selected using bit CH0–CH2,
the corresponding port C pin will read as a logic 0. The remaining port
C pins will read normally. To digitally read a port C pin, the A/D
subsystem must be disabled (ADON = 0), or input channels 5–7 must
be selected.
Table 9-1. A/D Multiplexer Input
Channel Assignments
Channel
Signal
0AD0 — port C, bit 6
1AD1 — port C, bit 5
2AD2 — port C, bit 4
3AD3 — port C, bit 3
4
VREFH — port C, bit 7
5
(VREFH + VSS)/2
6
VSS
7
Reserved for factory test
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