參數(shù)資料
型號： MCHC705P6ACSDR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER
文件頁數(shù)： 75/130頁
文件大?。?/td> 1541K
代理商： MCHC705P6ACSDR2
Interrupts
Interrupt Types
MC68HC705P6A — Rev. 2.0
Advance Information
MOTOROLA
Interrupts
49
$1FFA and $1FFB. If the port A interrupts are enabled by the MOR, they
generate external interrupts identically to the IRQ/VPP pin.
NOTE:
The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the
IRQ service routine.
Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.
5.3.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 8. Capture/Compare Timer. The input capture interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $1FF8 and $1FF9.
5.3.3.3 Output Compare Interrupt
The output compare interrupt is generated by a 16-bit timer as described
in Section 8. Capture/Compare Timer. The output compare interrupt
flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address is
specified by the contents of memory locations $1FF8 and $1FF9.
5.3.3.4 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in Section 8. Capture/Compare Timer. The timer overflow interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the timer overflow
interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.
相關(guān)PDF資料
PDF描述
MC68HC705P6AMP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6P 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6DW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6S 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
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