Pin Assignments and Reset States
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
9
FEC_CRS
PFECH0
ULPI_DIR
—
I
EVDD
—
B8
FEC_TXD[3:1]
PFECL[7:5]
ULPI_DATA[3:1]
—
O
EVDD
—
D3–D1
FEC_TXER
PFECL4
—
O
EVDD
—
B1
FEC_RXD[3:1]
PFECL[3:1]
ULPI_DATA[7:5]
—
I
EVDD
—
E7, A6, B6
FEC_RXER
PFECL0
—
I
EVDD
—
D4
LCD Controller
LCD_D17
PLCDDH1
CANTX
—
O
EVDD
—
C9
LCD_D16
PLCDDH0
CANRX
—
O
EVDD
—
D9
LCD_D17
PLCDDH1
—
O
EVDD
A6
C9
—
LCD_D16
PLCDDH0
—
O
EVDD
B6
D9
—
LCD_D15
PLCDDM7
—
O
EVDD
C6
A7
LCD_D14
PLCDDM6
—
O
EVDD
D6
B7
LCD_D13
PLCDDM5
—
O
EVDD
A5
C7
LCD_D12
PLCDDM4
—
O
EVDD
B5
D7
LCD_D[11:8]
PLCDDM[3:0]
—
O
EVDD
C5, D5, A4,
B4
D6, E6, A5,
B5
D6, E6, A5,
B5
LCD_D7
PLCDDL7
—
O
EVDD
C4
C5
LCD_D6
PLCDDL6
—
O
EVDD
B3
D5
LCD_D5
PLCDDL5
—
O
EVDD
A3
A4
LCD_D4
PLCDDL4
—
O
EVDD
A2
A3
LCD_D[3:0]
PLCDDL[3:0]
—
O
EVDD
D4, C3, D3,
B2
B4, C4, B3,
C3
B4, C4, B3,
C3
LCD_ACD/
LCD_OE
PLCDCTLH0
—
O
EVDD
D7
B9
LCD_CLS
PLCDCTLL7
—
O
EVDD
C7
A9
LCD_CONTRAST
PLCDCTLL6
—
O
EVDD
B7
D10
LCD_FLM/
LCD_VSYNC
PLCDCTLL5
—
O
EVDD
A7
C10
LCD_LP/
LCD_HSYNC
PLCDCTLL4
—
O
EVDD
A8
B10
LCD_LSCLK
PLCDCTLL3
—
O
EVDD
B8
A10
LCD_PS
PLCDCTLL2
—
O
EVDD
C8
A11
LCD_REV
PLCDCTLL1
—
O
EVDD
D8
B11
LCD_SPL_SPR
PLCDCTLL0
—
O
EVDD
B9
C11
Table 3. MCF5327/8/9 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Di
r.
1
Vo
lt
a
g
e
Domain
MCF5327
196
MAPBGA
MCF5328
256
MAPBGA
MCF53281
MCF5329
256
MAPBGA