MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Fr" />
參數(shù)資料
型號(hào): MCF5329CVM240
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 31/50頁(yè)
文件大小: 0K
描述: IC MCU 32BIT 240MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF532x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,PWM,WDT
輸入/輸出數(shù): 94
程序存儲(chǔ)器類(lèi)型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤(pán)
Electrical Characteristics
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
37
5.15
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.15.1
MII Receive Signal Timing
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_RXCLK frequency.
Table 23 lists MII receive channel timings.
Figure 23 shows MII receive signal timings listed in Table 23.
Figure 23. MII Receive Signal Timing Diagram
5.15.2
MII Transmit Signal Timing
Table 24 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_TXCLK frequency.
Figure 24 shows MII transmit signal timings listed in Table 24.
Table 23. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup
5
ns
M2
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
5
ns
M3
FEC_RXCLK pulse width high
35%
65%
FEC_RXCLK period
M4
FEC_RXCLK pulse width low
35%
65%
FEC_RXCLK period
Table 24. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
5
ns
M6
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
25
ns
M7
FEC_TXCLK pulse width high
35%
65%
FEC_TXCLK period
M8
FEC_TXCLK pulse width low
35%
65%
FEC_TXCLK period
M1
M2
FEC_RXCLK (input)
FEC_RXD[3:0] (inputs)
FEC_RXDV
FEC_RXER
M3
M4
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