MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 Fr" />
參數(shù)資料
型號(hào): MCF5329CVM240
廠商: Freescale Semiconductor
文件頁數(shù): 27/50頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 240MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF532x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,PWM,WDT
輸入/輸出數(shù): 94
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤
Electrical Characteristics
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Freescale Semiconductor
33
5.11
USB On-The-Go
The MCF5329 device is compliant with industry standard USB 2.0 specification.
5.12
ULPI Timing Specification
Control and data timing requirements for the ULPI pins are given in Table 18. These timings apply in synchronous mode only.
All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a
50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge.
The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.
Figure 19. ULPI Timing Diagram
5.13
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 18. ULPI Interface Timing
Parameter
Symbol
Min
Max
Units
Setup time (control in, 8-bit data in)
TSC, TSD
3.0
ns
Hold time (control in, 8-bit data in)
THC, THD
1.5
ns
Output delay (control out, 8-bit data out)
TDC, TDD
6.0
ns
Table 19. SSI Timing – Master Modes1
Num
Description
Symbol
Min
Max
Units
S1
SSI_MCLK cycle time2
tMCLK
8
× t
SYS
—ns
S2
SSI_MCLK pulse width high / low
45%
55%
tMCLK
S3
SSI_BCLK cycle time3
tBCLK
8
× t
SYS
—ns
S4
SSI_BCLK pulse width
45%
55%
tBCLK
S5
SSI_BCLK to SSI_FS output valid
15
ns
TSC
THC
TSD
TDC
TDD
ULPI_CLK
ULPI_STP
ULPI_DATA
ULPI_DIR/ULPI_NXT
ULPI_DATA
THD
(Output)
(Input)
(Input-8bit)
(Output-8bit)
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