IEEE 1149.1 Test Access Port (JTAG)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
21-3
21.3
TAP Controller
The TAP controller is a synchronous state machine that controls JTAG logic and interprets the sequence
of logical values on TMS. The value adjacent to each arrow in the state machine in
Figure 21-2 reflects
the value of TMS sampled on the rising edge of TCK. For a description of the TAP controller states, refer
to the IEEE 1149.1 document.
Figure 21-2. TAP Controller State Machine
TDI/DSI
Test and debug data in. Input provided for loading serial data port shift registers (boundary-scan, bypass, and
instruction registers). Shifting in of data depends on the state of the JTAG controller state machine and the
instruction currently in the instruction register. Data is shifted in on the rising edge of TCK.
TRST/
DSCLK
JTAG test reset. TRST asynchronously resets the JTAG TAP logic when low.
MTMOD
Freescale test mode select. Negating MTMOD enables JTAG mode; asserting it enables BDM mode.
Table 21-1. JTAG Signals (continued)
Signal
Description