Queued Serial Peripheral Interface (QSPI) Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
14-10
Freescale Semiconductor
Figure 14-4 shows an example of a QSPI clocking and data transfer.
Figure 14-4. QSPI Clocking and Data Transfer Example
13–10
BITS
Transfer size. Determines the number of bits to be transferred for each entry in the queue.
Value Bits per transfer
0000 16
0001– 0111 Reserved
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
9
CPOL
Clock polarity. Defines the clock polarity of SCK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
8
CPHA
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.
7–0
BAUD
Baud rate divider. The baud rate is selected by writing 0, or a value in the range 2–255. 1 is not a valid
value. A value of zero disables the QSPI. The desired QSPI_CLK baud rate is related to CLKIN and
QMR[BAUD] by the following expression:
QMR[BAUD] = SystemClock / [2
× (desired QSPI_CLK baud rate)]
Table 14-3. QMR Field Descriptions (continued)
Bits
Name
Description
QSPI_CLK
QSPI_Dout
QSPI_Din
QSPI_CS
A
B
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
msb