參數(shù)資料
型號: MCF5232
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Integrated Microprocessor Hardware Specification
中文描述: 集成的微處理器,硬件規(guī)格
文件頁數(shù): 5/60頁
文件大?。?/td> 1462K
代理商: MCF5232
Overview
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Preliminary
Freescale Semiconductor
5
1.3
Features
The following section gives a brief overview of this family’s feature set. For more detailed information see
the
MCF5235 Reference Manual
(MCF5235RM).
1.3.1
Feature Overview
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at twice the bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the
user stack pointer register, and 4 new instructions for improved bit processing
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
signal processing algorithms
— Illegal instruction decode that allows for 68K emulation support
Enhanced Time Processor Unit (eTPU)
— Event triggered VLIW processor timer subsystem
— 32 channels
— 24-bit timer resolution
— 6 Kbyte of code memory and 1.5 Kbyte of data memory
— Variable number of parameters allocatable per channel
— Double match/capture channels
— Angle mode support
— DMA and interrupt request support
— Nexus Class 1 Debug support
System debug support
— Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port
with cross triggering operations for ease of use
— Unified programming model including both ColdFire and Nexus debug registers
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
On-chip memories
— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
相關(guān)PDF資料
PDF描述
MCF5249 CodeWarrior Development Studio for ColdFire㈢ Architectures
MCF5251_07 ColdFire㈢ Microprocessor Data Sheet
MCF5251 ColdFire Processor
MCF5253 ColdFire㈢ Microprocessor Data Sheet
MCF5270AB100 Integrated Microprocessor Hardware Specification
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